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SOLVED: Consider an instruction pipeline with five stages without any branch prediction: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX), and Operand Write (OW). The stage delays for IF, ID, OF, EX, and OW are 5 ns, 7 ns, 10 ns, 8 ns, and 6 ns, respectively. There are intermediate storage buffers after each stage, and the delay of each buffer is 1 ns. A program consisting of 12 instructions I1, I2, ..., I12 is executed in the pipelined processor. Instruction I4
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