[SOLVED] - How do we set max fanout for clock nets
Aug 11, 2020 · Hello everyone, Could you show me how to set max fanout for clock nets in cadence innovus 18.1? Thanks so much!
What is a negative slack and how it affects timing?
Aug 12, 2006 · negative slack the negative slack has some reson , may the library is use to fix setup timing, this is a old method, now i think nobody use it. An other reason maybe the cell …
Difference between .sdc and .sdf files | Forum for Electronics
Feb 24, 2010 · The SDF file extension can be used as a schedule data file, a source definition file, a standard data format, a standard delay format, and a system data format. The SDF file …
help me to kill the process (cadence) | Forum for Electronics
Oct 28, 2005 · cadence + kill can anyone help me..i cannot edit my design (cadence) after my pc is hang,, after restart my pc i cannot edit my design,,anyone can help me what is the …
[SOLVED] - Eagle ULP script to convert kicad to eagle
Jun 7, 2007 · Hi John, Obviously this thread is really old, but I wanted to add this here to help out any other people searching for this. I've put together an improved Eagle to KiCAD schematic …
Is there a free eagle sch viewer to view the .brd and .sch files?
Oct 26, 2015 · Can anyone recommend free software to view the .brd and .sch files? Is there a free viewer for Eagle ? I have what should be a schematic file from a vendor, its suffix is .sch. I …
Importing netlist to Allegro PCB Designer warnings
Mar 18, 2013 · Welcome to EDAboard.com Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, …
[SOLVED] - Total Harmonic distortion in cadence
Jun 30, 2014 · Hi i need to calculate the THD in cadence for a multiplier circuit. I need to plot the TDH percent sweeping the two current inputs ix and iy. I searched online and found pss …
fifo with ram or flops | Forum for Electronics
Feb 16, 2014 · What is the impact of using ram vs flops for a fifo? I know ram can be smaller and so uses less power. What is the downside of using ram here?
What's NCVerilog Snapshot mean? | Forum for Electronics
May 23, 2004 · ncsim tutorial Hi all, I used to be a Modelsim user. Now my boss force me to use NCVerilog(seems very difficult to learn). We dump data from NCVerilog and view signal using …