Electronic Design

Predictive SoC Floorplanning Using Artificial Intelligence

Pain points of the existing floorplan designing process. How artificial intelligence can optimize this process to reduce the time taken from weeks to just hours. Potential applications of expanding ...
Nasdaq

Cadence Advances Hyperscale SoC Design with Expanded IP Portfolio for TSMC N3E Process Featuring Next-Generation 224G-LR SerDes IP

Proven interface IP architectures realized significant gains in performance and power efficiency on the TSMC N3E process 224G-LR SerDes PHY IP on the TSMC N3E process has achieved first-pass silicon ...
Electronic Design

Environment Speeds Platform-Based SoC Design And Verification

Getting the most from system-on-a-chip (SoC) designs requires optimal design of the logic surrounding the embedded processor. As SoCs have increased in complexity, optimizing the interfaces between ...
EDN

Why NoC tiling matters in AI-centric SoC designs

At a time when artificial intelligence (AI)-centric system-on-chips (SoCs) are growing in size and complexity, network-on-chip (NoC) tiling hand in hand with mesh topology can support faster ...
EDN

System-on-chip (SoC) design is all about IP management

For most system-on-chip (SoC) designs, the most critical task is not RTL coding or even creating the chip architecture. Today, SoCs are designed primarily by assembling various silicon intellectual ...