Semiconductor Engineering

Automate Memory Test Through A Shared Bus Interface

The use of memory-heavy IP in SoCs for automotive, artificial intelligence (AI), and processor applications is steadily increasing. However, these memory-heavy IP often have only a single access point ...
Semiconductor Engineering

Automation Of Shared Bus Memory Test With Tessent MemoryBIST

This paper describes the fundamental concepts and advantages of using a shared bus architecture for testing and repairing memories within IPs cores. It also outlines key features of the Tessent ...
TweakTown

MemTestX86 is here to help test for faulty DDR5 memory modules

PassMark is building its big update of MemTestX86, the first update since January 2022, which will support next-gen DDR5 memory. The creator of MemTestX86 took to Twitter to tease "a new era of memory ...
Electronic Design

The Challenges of Memory Mix Test

The variety of different test methodologies combined with today�s mixture of memory devices creates a complex test profile. The manufacturing test floor hums with activity; a range of memory devices ...
Business Wire

Keysight Introduces Comprehensive LPDDR6 Solution for End-to-End Memory Design and Test Workflows

Delivers complete design and validation solution for Low-Power Double Data Rate 6 (LPDDR6) memory in mobile, client computing, and AI applications. Supports JEDEC’s ongoing development of the new ...
Electronic Design

ATE – Design for Test – Putting Memory to the Test in Nanometer Designs

Memory test at-speed isn't easy but can be achieved by balancing test selection, area overhead, and test-time constraints. The semiconductor industry has intensified its focus on yield issues to meet ...