As integrated circuit (IC) designs continue to scale, the demand for efficient power management, performance optimization and reliable physical layout modification grows more critical. Meeting these ...

Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its usage on a 3 million-gate chip.

Reducing the layout-versus-schematic debug time while continuously delivering reliable, high-performance designs is a must for chip designers needing to meet tight tapeout deadlines and hopefully ...

In IC physical design, there is a tendency to focus on the synthesis and layout tasks, and to not give much consideration to the chip finishing tasks, at least not until the more pressing matters of ...

The right tool for the job makes all the difference. Ever try hammering a nail in with a rock? How many nails did you ruin before you gave up? Or try to tighten a crucial bolt by hand? It takes ...